High-speed, multichannel D/A platform equipped with a Virtex-4 FPGA
The VHS-DAC is a high-speed, multichannel D/A conversion advanced development platform. It is equipped with eight phase-synchronous D/A converters that operate at a maximum refresh rate of 480 MSPS through on-chip interpolation and a high-capacity FPGA for high-speed processing. It is perfect for multichannel IF signal generation (with the AC-coupled option) or baseband signal generation (with the DC-coupled option), among other applications.
Highlights
- Onboard, 8-channel, 480 MSPS, 14-bit D/A converters on 6U cPCI (PXI compatible)
- Mezzanine expansion site to support more channels or memory
- Sustained, 8 Gbps, raw data RX/TX RapidCHANNEL ports (one each)
- Model-based design flow support
Applications/Fields
Telecommunications
- Base transceiver stations
- Broadcasting
- Routers
- Triple play
- Quadruple play
- Adaptive beamformers
- MIMO
- Software-defined radio
Military and aerospace
- Digital communications
- Target tracking
- Software-defined radio
Medical imaging
- Positron emission tomography
- Gamma ray detection
- Ultrasound
Industrial
- Testing
- Instrumentation
- Storage
- Channel simulation
- Channel analysis
Characteristics
Form factors
- 6U cPCI
- 6U PXI
Functions
- A/D conversion
- Digital signal processing
- Multichannel storage/playback
FPGA
- XC4VLX100
- XC4VLX160
- XC4VSX55
Literature
Technical specs
Demos
MIMO FlexOFDM demo
Help file of the Simulink model supplied with the demo (license sold separately).
Model-based positron emission tomography demo
Help file of the Simulink model supplied with the MBDK.
White papers
Frequency-domain characterization of broadband indoor MIMO channels using a 4x4 testbed
Prototyping a MIMO W-CDMA system using a system-level approach
FPGA electronics for OPET: A dual-modality optical and PET imaging tomography
Designing an FPGA-based MIMO transceiver for Wi-Fi
Architecture of a on-chip, high-resolution, fully digital PET scanner for small animal imaging
Baseband algorithms: Implementation and integration (MIMAX)
Improved Data Acquisition System for Brain PET Using GAPD Arrays
Free-running ADC and FPGA-based signal processing method for brain PET using GAPD arrays
Success stories
Success Story - Digital LLRF for Alba storage ring
Success Story – Los Alamos National Laboratory
The Generic Hardware Demonstrator for MIMO Systems (GEDOMIS) hosts a real-time implementation of the IEEE 802.16e-2005 physical layer featuring a 2×2 MIMO configuration and a high 20 MHz bandwidth. The algorithms of the mobile WiMAX receiver were modeled with MATLAB, designed with custom VHDL and implemented in FPGA devices operating in real-time using Lyrtech’s VHS-ADC and SignalMaster Quad. The VHDL code was integrated to the target boards with Lyrtech's own BSDK. For details about GEDOMIS, click here or view the GEDOMIS video on the Multimedia tab.
Software development tools
Software development tools
- Board software development kit (included)
- Model-based design kit (optional)
- Diamond (optional)
Downloads
Multimedia
MIMO FlexOFDM demo
Model-based design implementation of a flexible MIMO OFDM testbed (FlexOFDM)
GEDOMIS
The Generic Hardware Demonstrator for MIMO Systems (GEDOMIS) hosts a real-time implementation of the IEEE 802.16e-2005 physical layer featuring a 2×2 MIMO configuration and a high 20 MHz bandwidth. The algorithms of the mobile WiMAX receiver were modeled with MATLAB, designed with custom VHDL and implemented in FPGA devices operating in real-time using Lyrtech’s VHS-ADC and SignalMaster Quad. The VHDL code was integrated to the target boards with Lyrtech's own BSDK. For details about GEDOMIS, click here.
Documentation
Specification sheet - VHS-DAC (hi_res).pdfSpecification sheet - VHS-DAC (lo_res).pdfRelated productsSupport
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