Lyrtech RD - ADACSync - 6U cPCI, multichannel, GPS-disciplined, precision clock generator

ADACSync

6U cPCI, multichannel, GPS-disciplined, precision clock generator

The ADACSync is a 6U, cPCI (PXI compatible), GPS-disciplined, precision low-jitter clock generator specifically designed to help synchronize multichannel system clocks, such as when synchronizing several digitizer boards or daisy chaining ADACSyncs to yield more channels (with an external input clock).
The ADACSync is also equipped of a GPS module, enabling the onboard VCxO to continuously match the GPS reference (a process referred to as "GPS-disciplined clock"). The GPS position/time information is also available for DAQ applications.

Highlights

Five, independent programmable clock outputs
Output range from 31.25 MHz to 350.00 MHz
Less than 0.1 ppm, GPS-matched, onboard reference 10 MHz VCxO
Distribution buffer with eight frequency-synchronous channels (programmable CLK0)
Four, independently buffered outputs (programmable CLK1–CLK4)
Reference clocks—External, onboard, or onboard GPS disciplined
1 pps GPS outputs
GPS time/position-stamp at GPIO-32 output
Stand-alone configuration through the onboard EEPROM
Easy-to-use programming application

Applications/Fields

Telecommunications

MIMO
802.11n
Adaptive beamformers
Base transceiver stations
Routers
Triple play
Quadruple play
Software-defined radio
WCDMA
WiMAX

Military and aerospace

Digital communications
Software-defined radio

Medical imaging

Positron emission tomography
Gamma ray detection

Industrial

Channel analysis
Channel simulation

Characteristics

Form factors

6U cPCI
6U PXI

Functions

Clock generation
Clock distribution
GPS reference clock
GPS time/data stamping

LITERATURE

Demos

MIMO FlexOFDM demo

Help file of the Simulink model supplied with the demo (license sold separately).

Whitepapers

Frequency-domain characterization of broadband indoor MIMO channels using a 4x4 testbed

Success stories

Gedomis

The Generic Hardware Demonstrator for MIMO Systems (GEDOMIS) hosts a real-time implementation of the IEEE 802.16e-2005 physical layer featuring a 2×2 MIMO configuration and a high 20 MHz bandwidth. The algorithms of the mobile WiMAX receiver were modeled with MATLAB, designed with custom VHDL and implemented in FPGA devices operating in real-time using Lyrtech’s VHS-ADC and SignalMaster Quad. The VHDL code was integrated to the target boards with Lyrtech's own BSDK. For details about GEDOMIS, click here.